In writing data in a semiconductor device, e.g., a memory, input data bits are usually received in series from a memory controller, converted to parallel data bits and then stored in the device. This may require latching of multiple data bits that are input in series. For example, data with a 16-bit burst length in a single DQ may be latched four bits at a time, each latch provides four output bits in parallel. In order to latch four bits that come in series, the data input circuit may include one or more delay circuits to delay one or more data bits so that all of the four bits are aligned and ready to be latched at the same time. These added delay circuits, along with other circuits that may be required to convert serial data bits to parallel bits may result in complexity of circuits in the semiconductor device and increase the power consumption of the device.